The advent of virtual storage for computer systems has increased the desirability of using a large virtual address. In addition to providing enough bits in an address to reference the main store, it is desirable to provide a single large address having sufficient bits to reference all of secondary storage, e.g., disks, drums, and bubble memories. In the past, large virtual addresses could only be implemented practically on systems having a central processing unit ("CPU") with wide data paths (i.e., wide enough to pass all of the bits in a large virtual address in parallel), a wide arithmetic and logic unit ("ALU"), and wide local storage register ("LSR") arrays. However, the cost of the hardware required for such an implementation is prohibitive for a small computer system. Therefore, the usual approach for implementation of a large virtual address on a small computer system is to provide narrow data paths, a narrow ALU, and narrow LSR arrays and to make multiple passes through the CPU in order to operate on addresses wider than the data paths, ALU, and LSR arrays. These multiple passes result in significant performance degradation, and consequently the implementation of a large virtual address on a small computer system by this approach is impractical.
The usual performance degradation resulting from the implementation of a large virtual address on a small computer system is eliminated by the present invention. Implementation of a large virtual address is facilitated by splitting the base address registers into segment registers and offset registers so as to eliminate the need for the segment portion of the virtual addresses to participate in arithmetic operations. Thus, narrow data paths (i.e., narrow in the sense that the data paths carry fewer bits of data simultaneoulsy in parallel), a narrow ALU, and narrow LSR arrays can be utilized in the CPU to implement a large virtual address on a small computer system without casing performance degredation.
The prior art, U.S. Pat. No. 3,938,096--Brown et al., discloses an address having a base segment and an offset within the segment. However, Brown et al. does not teach splitting the segment away from the offset so that only the offset participates in arithmetic operations to increment or decrement an address.